1. Field of the Invention
This invention relates to a reference circuit. More specifically, this invention relates to a reference circuit for high speed memories which provides a greater margin for access time and noise levels over a range of temperatures and supply voltages.
2. Background Information
In order to increase the yield of low access time memories, device speeds can be increased by varying process parameters. Accordingly, the speeds of the slower memories in the yield distribution are increased and there is a higher yield of memory devices with low access times. When device speeds are increased, however, the speeds of the fastest of the memories in the yield distribution are also increased. As a result, the fastest memories become so fast that they suffer from ground bounce problems under ideal speed operating conditions. The total yield of memory devices which function over a specified operating voltage and temperature range is therefore not increased as much as desired.
The speed of CMOS and Bi-CMOS devices is fastest at high supply voltages and at low operating temperatures. Accordingly, if device speeds are increased to increase the yield of high speed CMOS and Bi-CMOS memories, the fastest CMOS and Bi-CMOS memory devices suffer from ground bounce problems when their operating supply voltages are high and when their operating temperatures are low.
To explain the operation of the present invention, the operation of one known type of a band gap reference circuit, the band gap reference circuit shown in FIG. 1, is described. The purpose of this circuit is to generate an output reference voltage V.sub.REF, the magnitude of which does not vary with temperature. This is accomplished by generating a voltage KV.sub.T with a positive temperature coefficient and then adding that voltage to the base-emitter voltage V.sub.be(on) of a transistor which has a negative temperature coefficient. If the magnitude of the positive temperature coefficient voltage KV.sub.T is properly chosen, the resulting summation V.sub.REF of the two voltages V.sub.be(on) and KV.sub.T will have an overall zero temperature coefficient as shown below in equation 1. EQU V.sub.REF =V.sub.be(on) +KV.sub.T (Equ. 1)
V.sub.be(on) typically has a negative temperature coefficient of approximately -2 mV/.degree.C. whereas V.sub.T typically has a positive temperature coefficient of approximately 0.085 mV/.degree.C.
The band gap circuit of FIG. 1 (Prior Art) comprises two bipolar transistors Q0 and Q1 which form a current mirror with two collector currents I.sub.CQ0 and I.sub.CQ1 flowing through the two transistors Q0 and Q1, respectively. The base of transistor Q0, the base of transistor Q1, and the collector of transistor Q1 are connected together at node N1. The emitter of transistor Q1 is tied directly to ground, whereas the emitter of transistor Q0 is tied to ground through a resistor R6. Due to the inclusion of resistor R1 between the emitter of transistor Q0 at node N5 and ground, the proportion of current passing through transistor Q0 can be chosen to be any fraction of the current passing through transistor Q1. The voltage present across the base emitter junction of transistor Q0 is always related to, yet always smaller than, the voltage present across the base emitter junction of transistor Q1.
Similarly, the relative sizes of Q1 and Q0 can be varied so that Q0 conducts more current at a given base-emitter voltage than Q1 conducts at the same base-emitter voltage. Current I.sub.CQ0 can therefore be chosen to be larger than, equal to, or smaller than current I.sub.CQ1 as long as variations in current I.sub.CQ1 affect corresponding changes in current I.sub.CQ0.
Assuming, for the time being, that a constant temperature independent voltage exists at node N0. The voltage dropped across resistor R2 increases with temperature because the voltage V.sub.be across the base-emitter junction of the diode-connected transistor Q1 decreases with temperature. With a larger voltage dropped across R2 as temperature increases, a larger current I.sub.R2 flows across resistor R2 as temperature increases. Resistor R4 is provided between Vcc and node N4 to bias node N4 initially so that the base-emitter junctions of transistors Q2 and Q3 will be forward biased thereby causing the circuit to reach a stable operating point. Additional details of such a band-gap reference voltage supply circuit are given in Analysis and Design of Analog Integrated Circuits (second ed. 1984) by Paul Gray and Robert Meyer, pages 289-296.
The current I.sub.CQ0 flowing into the collector of transistor Q0 will be the mirror of current I.sub.R2 and therefore must also have a positive temperature coefficient. Assuming that a negligible amount of current flows into the base of the transistor Q4, current I.sub.CQ0 is converted into a voltage with a positive temperature coefficient by running current I.sub.CQ0 through a resistor R3. One end of resistor R3 is connected to the collector of transistor Q0 at a node N2. The other end of resistor R3 is connected to a node N3. The resistance of resistor R3 is therefore seen to influence the magnitude of the constant K in the voltage KV.sub.T. This voltage has a positive temperature coefficient across resistor R3.
To add a negative temperature coefficient voltage to the positive temperature coefficient voltage across resistor R3, the base of bipolar transistor Q4 is connected to node N2 and the emitter of bipolar transistor Q4 is connected to ground. Accordingly, the base-emitter voltage V.sub.be(on) of transistor Q4 will be present between ground and node N2. The voltage at node N3 therefore is the sum of the negative temperature coefficient voltage V.sub.be(on) from ground to node N2 and the positive temperature coefficient voltage KV.sub.T across resistor R3. By properly choosing the magnitude of resistor R3, the magnitude of the positive temperature coefficient voltage drop across resistor R3 can be chosen to cancel exactly the negative temperature coefficient of V.sub.be(on) of transistor Q4. The bandgap reference voltage output V.sub.REF of the circuit of FIG. 1 is therefore present between node N3 and ground.
This conclusion is, however, premised on the voltage N0 being a constant temperature independent voltage. By connecting the emitter of a transistor Q2 to node N0, by connecting the base of transistor Q2 to the base of a transistor Q3, by connecting the emitter of transistor Q3 to the temperature compensated node N3, and by connecting the collectors of transistors Q2 and Q3 to Vcc, node N4 is biased at one base-emitter drop above the voltage on node N3 so that the voltage on node N0 is biased at one base-emitter voltage drop below the voltage on node N4. The result is that node N0 is supplied with temperature independent voltage on node N3 as previously assumed.
If the bandgap reference circuit of FIG. 1 were used to supply current to a CMOS or Bi-CMOS memory, the reference circuit would output a constant current as the circuit temperature decreased. The CMOS or Bi-CMOS memory circuitry would therefore become faster and the fastest memories in the yield distribution may suffer from ground bounce problems.